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FS6131
Programmable Line Lock Clock Generator IC
1.0 Key Features
* * * * Complete programmable control via I2CTM-bus Selectable CMOS or PECL compatible outputs External feedback loop capability allows genlocking Tunable VCXO loop for jitter attenuation
2.0 General Description
The FS6131-01 is a monolithic CMOS clock generator/regenerator IC designed to minimize cost and component count in a variety of 2 electronic systems. Via the I C-bus interface, the FS6131-01 can be adapted to many clock generation requirements. The ability to tune the on-board voltage-controlled crystal oscillator (VCXO), the length of the reference and feed-back dividers, their granularity, and the flexibility of the post divider make the FS6131-01 the most flexible stand-alone phase-locked loop (PLL) clock generator available.
3.0 Applications
* * * * Frequency synthesis Line-locked and genlock applications Clock multiplication Telecom jitter attenuation
SCL SDA ADDR VSS XIN XOUT XTUNE VDD
1 2 3
16 15 14
CLKN CLKP VDD FBK REF VSS EXTLF LOCK/IPRG
FS6131
4 5 6 7 8
13 12 11 10 9
16-pin 0.150" SOIC
Figure 1: Pin Configuration
(c)2008 SCILLC. All rights reserved. May 2008 - Rev. 4
Publication Order Number: FS6131/D
FS6131
LFTC
CLF CLP
XTUNE
(optional)
XCT[3:0], XLVTEN
Control ROM VCXO Divider
XLROM[2:0] XLPDEN, XLSWAP
CRYSTAL LOOP
XLCP[1:0]
XIN VCXO XOUT
(optional)
Internal Loop Filter
0 EXTLF STAT[1:0] 1
RLF
PhaseFrequency Detector
UP
EXTLF
(optional)
Charge Pump
DOWN
Lock Detect
REFDIV[11:0]
CMOS 1
0 POST3[1:0] POST2[1:0] POST1[1:0]
LOCK/ IPRG
(optional)
REF
0 1 REFDSRC
(fREF)
Reference Divider
(NR)
MLCP[1:0] 0 PDREF UP
VCOSPD, OSCTYPE
GBL
11
1
FBK
1 0 PDFBK
PhaseFrequency Detector
Charge Pump
DOWN
Voltage Controlled Oscillator
01 00 10
Clock Gobbler
OUTMUX[1:0]
Post Divider (NPx) CMOS/PECL Output
CLKP
(fCLK)
CLKN
ADDR Feedback Divider (NF) SCL SDA I2C Interface Registers
FBKDIV[13:0]
11 01 10 00 FBKDSRC[1:0]
(fVCO)
MAIN LOOP
FS6131
Figure 2: Block Diagram
Table 1: Pin Descriptions
Key: AI = Analog Input; AO = Analog Output; DI = Digital Input; DIU = Input with Internal Pull-Up; DID = Input with Internal Pull-Down; DIO = Digital Input/Output; DI-3 = Three-Level Digital Input, DO = Digital Output; P = Power/Ground; # = Active Low pin
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Type DI DIO DI P AI AO AI P DIO AI P DI DI P DO DO Name SCL SDA ADDR VSS XIN XOUT XTUNE VDD LOCK/IPRG EXTLF VSS REF FBK VDD CLKP CLKN Description Serial interface clock (requires an external pull-up) Serial interface data input/output (requires an external pull-up) Address select bit (see Section 5.2.1) Ground VCXO feedback VCXO drive VCXO tune Power supply (+5V) Lock indicator / PECL current drive programming External loop filter Ground Reference frequency input Feedback input Power supply (+5V) Differential clock output (+) Differential clock output (-)
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FS6131
4.0 Functional Block Description
4.1 Main Loop PLL The main loop phase locked loop (ML-PLL) is a standard phase- and frequency- locked loop architecture. As shown in Error! Reference source not found., the ML-PLL consists of a reference divider, a phase-frequency detector (PFD), a charge pump, an internal loop filter, a voltage-controlled oscillator (VCO), a feedback divider, and a post divider. During operation, the reference frequency (fREF), generated by either the on-board crystal oscillator or an external frequency source, is first reduced by the reference divider. The integer value that the frequency is divided by is called the modulus, and is denoted as NR for the reference divider. The divided reference is then fed into the PFD. The PFD controls the frequency of the VCO (fVCO) through the charge pump and loop filter. The VCO provides a high-speed, low noise, continuously variable frequency clock source for the ML-PLL. The output of the VCO is fed back to the PFD through the feedback divider (the modulus is denoted by NF) to close the loop. The PFD will drive the VCO up or down in frequency until the divided reference frequency and the divided VCO frequency appearing at the inputs of the PFD are equal. The input/output relationship between the reference frequency and the VCO frequency is
fVCO f = REF NF NR
If the VCO frequency is used as the PLL output frequency (fCLK) then the basic PLL equation can be rewritten as
N f CLK = f REF F N R
4.1.1. Reference Divider The reference divider is designed for low phase jitter. The divider accepts either the output of either the crystal loop (the VCXO output) or an external reference frequency, and provides a divided-down frequency to the PFD. The reference divider is a 12-bit divider, and can be programmed for any modulus from 1 to 4095. See both Table 3 and Table 8 for additional programming information.
4.1.2. Feedback Divider The feedback divider is based on a dual-modulus pre-scaler technique. The technique allows the same granularity as a fully programmable feedback divider, while still allowing the programmable portion to operate at low speed. A high-speed pre-divider (also called a prescaler) is placed between the VCO and the programmable feedback divider because of the high speeds at which the VCO can operate. The dual-modulus technique insures reliable operation at any speed that the VCO can achieve and reduces the overall power consumption of the divider. For example, a fixed divide-by-eight could be used in the feedback divider. Unfortunately, a divide-by-eight would limit the effective modulus of the feedback divider path to multiples of eight. The limitation would restrict the ability of the PLL to achieve a desired inputfrequency-to-output frequency ratio without making both the reference and feedback divider values comparatively large. Large divider moduli are generally undesirable due to increased phase jitter.
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FS6131
fvco
DualModulus Prescaler
M Counter
A Counter
Figure 3: Feedback Divider
To understand the operation, refer to Error! Reference source not found.. The M-counter (with a modulus of M) is cascaded with the dual-modulus pre-scaler. If the prescaler modulus were fixed at N, the overall modulus of the feedback divider chain would be MXN. However, the A-counter causes the pre-scaler modulus to be altered to N+1 for the first A outputs of the pre-scaler. The A-counter then causes the dual-modulus prescaler to revert to a modulus of N until the M-counter reaches its terminal state and resets the entire divider. The overall modulus can be expressed as
A( N + 1) + N ( M - A)
where M A, which simplifies to
M xN + A
4.1.3. Feedback Divider Programming The requirement that M A means that the feedback divider can only be programmed for certain values below a divider modulus of 56. The selection of divider values is listed in Table 2. If the desired feedback divider is less than 56, find the divider value in the table. Follow the column up to find the A-counter program value. Follow the row to the left to find the M-counter value. Above a modulus of 56, the feedback divider can be programmed to any value up to 16383. See both Table 3 and Table 8 for additional programming information.
Table 2: Feedback Modulus Below 56 M-Counter: FBKDIV[13:3] 00000000001 00000000010 00000000011 00000000100 00000000101 00000000110 00000000111 A-counter: FBKDIV[2:0] 000 8 16 24 32 40 48 56 001 9 17 25 33 41 49 57 010 18 26 34 42 50 58 011 27 35 43 51 59 100 36 44 52 60 101 45 53 61 110 54 62 111 63
Feedback Divider Modulus
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FS6131
4.1.4. Post Divider The post divider consists of three individually programmable dividers, as shown in Error! Reference source not found..
POST1[1:0]
POST2[1:0]
POST3[1:0]
fGBL
Post Divider 1 (NP1)
Post Divider 2 (NP2)
POST DIVIDER (NPx)
Post Divider 3 (NP3)
fout
Figure 4: Post Divider
The moduli of the individual dividers are denoted as NP1, NP2, and NP3, and together they make up the array modulus NPx.
N Px = N P1 x N P 2 x N P 3
The post divider performs several useful functions. First, it allows the VCO to be operated in a narrower range of speeds compared to the variety of output clock speeds that the device is required to generate. Second, it changes the basic PLL equation to
N 1 f CLK = f REF F N N R Px
The extra integer in the denominator permits more flexibility in the programming of the loop for many applications where frequencies must be achieved exactly. Note that a nominal 50/50 duty factor is preserved for selections which have an odd modulus.
4.2 Phase Adjust and Sampling In line-locked or genlocked applications, it is necessary to know the exact phase relation of the output clock relative to the input clock. Since the VCO is included within the feedback loop in a simple PLL structure, the VCO output is exactly phase aligned with the input clock. Every cycle of the input clock equals NR/NF cycles of the VCO clock.
fIN
Reference Divider (NR)
Phase Frequency Detect
VCO
fOUT
fIN fOUT
Feedback Divider (NF)
Figure 5: Simple PLL
The addition of a post divider, while adding flexibility, makes the phase relation between the input and output clock unknown because the post divider is outside the feedback loop.
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FS6131
fIN
Reference Divider (NR)
Phase Frequency Detect
VCO
Post Divider (NF)
fOUT
fIN fVCO fOUT
?
Feedback Divider (NF)
fVCO
Figure 6: PLL with Post Divider
4.2.1. Clock Gobbler (Phase Adjust) The clock gobbler circuit takes advantage of the unknown relationship between input and output clocks to permit the adjustment of the CLKP/CLKN output clock phase relative to the REF input. The clock gobbler circuit removes a VCO clock pulse before the pulse clocks the post divider. In this way, the phase of the output clock can be slipped until the output phase is aligned with the input clock phase. To adjust the phase relationship, switch the feedback divider source to the post divider input via the FBKDSRC bit, and toggle the GBL register bit. The clock gobbler output clock is delayed by one VCO clock period for each transition of the GBL bit from zero to one.
4.2.2. Phase Alignment To maintain a fixed phase relation between input and output clocks, the post divider must be placed inside the feedback loop. The source for the feedback divider is obtained from the output of the post divider via the FBKDSRC switch. In addition, the feedback divider must be dividing at a multiple of the post divider.
fIN
Reference Divider (NR)
Phase Frequency Detect
VCO
Post Divider (NF)
fOUT
fIN fOUT
Feedback Divider (NF)
Figure 7: Aligned I/O Phase
4.2.3. Phase Sampling and Initial Alignment However, the ability to adjust the phase is useless without knowing the initial relation between output and input phase. To aid in the initial synchronization of the output phase to input phase, a phase align "flag" makes a transition (zero to one or one to zero) when the output clock phase becomes aligned with the feedback source phase. The feedback source clock is, by definition, locked to the input clock phase.
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FS6131
First, the FS6131 is used to sample the output clock with the feedback source clock and set/clear the phase align flag when the two clocks match to within a feedback source clock period. Then, the clock gobbler is used to delay the output phase relative to the input phase one VCO clock at a time until a transition on the flag occurs. When a transition occurs, the output and input clocks are phase aligned. To enter this mode, set STAT[1] to one and clear STAT[0] to zero. If the CMOS bit is set to one, the LOCK/IPRG pin can display the flag. The flag is always available under software control by reading back the STAT[1] bit, which will be overwritten by the flag in this mode.
4.2.4. Feedback Divider Monitoring The feedback divider clock can be brought out the LOCK/IPRG pin independent of the output clock to allow monitoring of the feedback divider clock. To enter this mode, set both the STAT[1] and STAT[0] bits to one. The CMOS bit must also be set to one to enable the LOCK/IPRG pin as an output.
4.3 Loop Gain Analysis For applications where an external loop filter is required, the following analysis example can be used to determine loop gain and stability. The loop gain of a PLL is the product of all of the gains within the loop.
The transfer function of the phase detector and charge pump combination is (in A/rad):
K PD =
The transfer function of the loop filter is (in V/A):
I chgpump 2
K LF ( s ) =
1 1 sC 2 + R + 1 LF sC 1
The VCO transfer function (in rad/s, and accounting for the phase integration that occurs in the VCO) is:
K VCO ( s ) = 2AVCO
1 s
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FS6131
The transfer function of the feedback divider is:
KF =
1 NF
Finally, the sampling effect that occurs in the phase detector is accounted for by:
- s 1 - e f REF K SAMP ( s ) = f REF s
The loop gain of the PLL is:
K LOOP ( s ) = K PD K LF ( s ) K VCO ( s ) K F K SAMP ( s )
100
10
Amplitude
1
0.1
0.01 0.1kHz
1kHz
10kHz
100kHz
Frequency (fi)
Figure 8: Loop Gain vs. Frequency
The loop phase angle is:
i = arg K LOOP ( j 2f i )
[
]
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FS6131
-100
Phase
-150 0.1kHz
1kHz
10kHz
100kHz
Frequency (fi)
Figure 9: Loop Nyquist Plot
A Nyquist plot of gain vs. amplitude is shown below.
90 1.2 1.0 135 0.8 45
Amplitude
0.6 0.4 0.2
Gain Margin
180 0
Phase Margin
225
315
270
Phase
Figure 10: Loop Nyquist Plot
4.4 Voltage-Controlled Crystal Oscillator The VCXO provides a tunable, low-jitter frequency reference for the rest of the FS6131 system components. Loading capacitance for the crystal is internal to the device. No external components (other than the resonator itself) are required for operation of the VCXO. The resonator loading capacitance is adjustable under register control. This feature permits factory coarse tuning of inexpensive resonators to the necessary precision for digital video applications. Continuous fine-tuning of the VCXO frequency is accomplished by
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FS6131
varying the voltage on the XTUNE pin. The total change (from one extreme to the other) in effective loading capacitance is 1.5pF nominal, and the effect is shown in Error! Reference source not found.. The oscillator operates the crystal resonator in the parallelresonant mode. Crystal warping, or the "pulling" of the crystal oscillation frequency, is accomplished by altering the effective load capacitance presented to the crystal by the oscillator circuit. The actual amount that changing the load capacitance alters the oscillator frequency will be dependent on the characteristics of the crystal as well as the oscillator circuit itself. The motional capacitance of the crystal (usually referred to by crystal manufacturers as C1), the static capacitance of the crystal (C0) and the load capacitance (CL) of the oscillator determine the warping capability of the crystal in the oscillator circuit. A simple formula to determine the total warping capability of a crystal is
f ( ppm) =
6 C1 x (C L 2 - C L1) x 10 2 x (C 0 + C L 2 ) x (C 0 + C L1)
where CL1 and CL2 are the two extremes of the applied load capacitance obtained from Table 11. Example: A crystal with the following parameters is used with the FS6131. The total coarse tuning range is: C1=0.02pF, C0=5.0pF, CL1=10.0pF, CL2=22.66pF
f =
0.02 x (22.66 - 10 ) x 10 6 = 305 ppm 2 x (5 + 22.66 ) x (5 + 10 )
4.4.1. VCXO Tuning The VCXO may be coarse tuned by a programmable adjustment of the crystal load capacitance via the XCT[3:0] control bits. See Table 11 for the control code and the associated loading capacitance. The actual amount of frequency warping caused by the tuning capacitance will depend on the crystal used. The VCXO tuning capacitance includes an external 6pF load capacitance (12pF from the XIN pin to ground and 12pF from the XOUT pin to ground). The fine tuning capability of the VCXO can be enabled by setting the XLVTEN bit to a one, or disabled by setting it to a zero. Error! Reference source not found. shows the typical effect of the coarse and fine tuning mechanisms. The total coarse tune range is about 350ppm. The difference in VCXO frequency in parts per million (ppm) is shown as the fine tuning voltage on the XTUNE pin varies from 0V to 5V. Note that as the crystal load capacitance is increased the VCXO frequency is pulled somewhat less with each coarse step, and the fine tuning range decreases. The fine tuning range always overlaps a few coarse tuning ranges, eliminating the possibility of holes in the VCXO response. The different crystal warping characteristics may change the scaling on the Y-axis, but not the overall characteristic of the curves.
VCXO Range (ppm) vs. XTUNE Voltage (V)
200 150
VCXO Range (ppm)
XTUNE Voltage = 0.0V XTUNE Voltage = 5.0V
100 50 0 -50 -100 -150 -200
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
Coarse Tune Setting XCT[3:0]
Figure 11: VCXO Course and Fine Tuning
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FS6131
4.5 Crystal Loop The crystal loop is designed to attenuate the jitter on a highly jittered, low-Q, low frequency reference. The crystal loop can also maintain a constant frequency output into the main loop if the low frequency reference is intermittent. The crystal loop consists of a voltage-controllable crystal oscillator (VCXO), a divider, a PFD, and a charge pump that tunes the VCXO to a frequency reference. The frequency reference is phase-locked to the divided frequency of an external, high-Q, jitter-free crystal, thereby locking the VCXO to the reference frequency. The VCXO can continue to run off the crystal even if the frequency reference becomes intermittent. 4.5.1. Locking to an External Frequency Source When the crystal loop is synchronized to an external frequency source, the FS6131 can monitor the crystal loop and detect if the loop unlocks from the external source. The crystal loop tries to drive to zero frequency if the external source is dropped, and sets a lock status error flag. The crystal loop can also detect if the VCXO has dropped out of the fine tune range, requiring a change to the coarse tune. The lock status also latches the direction the loop went out of range (high or low) when the loop became unlocked. 4.5.1.1 Crystal Loop Lock Status Flag To enable this mode, clear the STAT[1] and STAT[0] bits to zero. If the CMOS bit is set to one, the LOCK/IPRG pin will be low if the crystal loop becomes unlocked. The flag is always available under software control by reading back the STAT[1] bit, which is overwritten with the status flag (low = unlocked) in this mode (see Table 6).
4.5.1.2 Out-Of-Range High/Low
The direction the loop has gone out-of-range can be determined by clearing STAT[1] to zero and setting STAT[0] bit to one. If the CMOS bit is set to one, the LOCK/IPRG pin will go high if the crystal loop went out of range high. If the pin goes to a logic-low, the loop went out of range low. The out-of-range information is also available under software control by reading back the STAT[1] bit, which is overwritten by the flag (high = outof-range high, low = out-of-range low) in this mode. The bit is set or cleared only if the crystal loop loses lock (see Table 6).
4.5.1.3 Crystal Loop Disable
The crystal loop is disabled by setting the XLPDEN bit to a logic-high (1). The bit disables the charge pump circuit in the loop. Setting the XLPDEN bit low (0) permits the crystal loop to operate as a control loop. 4.6 Connecting the FS6131 to an External Reference Frequency If a crystal oscillator is not used, tie XIN to ground and shut down the crystal oscillator by setting XLROM[2:0]=1. The REF and FBK pins do not have pull-up or pull-down current, but do have a small amount of hysteresis to reduce the possibility of extra edges. Signals may be AC-coupled into these inputs with an external DC-bias circuit to generate a DC-bias of 2.5V. Any reference or feedback signal should be square for best results, and the signals should be rail-to-rail. Unused inputs should be grounded to avoid unwanted signal injection. 4.7 Differential Output Stage The differential output stage supports both CMOS and pseudo-ECL (PECL) signals. The desired output interface is chosen via the program registers (see Table 4). If a PECL interface is used, the transmission line is usually terminated using a Thevenin termination. The output stage can only sink current in the PECL mode, and the amount of sink current is set by a programming resistor on the LOCK/IPRG pin. The ratio of IPRG current to output drive current is shown in Figure 12. Source current is provided by the pull-up resistor that is part of the Thevenin termination.
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FS6131
25.0
IPRG Input Current (mA)
20.0
15.0
10.0
5.0
0.0 0 20 40 60 80
CLKP/CLKN PECL Output Current (mA)
Figure 12: IPRG to CLKP/CLKN Current
5.0 I2C-bus Control Interface
This device is a read/write slave device meeting all Philips I2C-bus specifications except a "general call." The bus has to be controlled by a master device that generates the serial clock SCL, controls bus access and generates the START and STOP conditions while the device works as a slave. Both master and slave can operate as a transmitter or receiver, but the master device determines which mode is activated. A device that sends data onto the bus is defined as the transmitter, and a device receiving data as the receiver. I2C-bus logic levels noted herein are based on a percentage of the power supply (VDD). A logicone corresponds to a nominal voltage of VDD, while a logic-zero corresponds to ground (VSS).
5.1 Bus Conditions Data transfer on the bus can only be initiated when the bus is not busy. During the data transfer, the data line (SDA) must remain stable whenever the clock line (SCL) is high. Changes in the data line while the clock line is high will be interpreted by the device as a START or STOP condition. The following bus conditions are defined by the I2C-bus protocol.
5.1.1. Not Busy Both the data (SDA) and clock (SCL) lines remain high to indicate the bus is not busy.
5.1.2. START Data Transfer A high to low transition of the SDA line while the SCL in-put is high indicates a START condition. All commands to the device must be preceded by a START condition.
5.1.3. STOP Data Transfer A low to high transition of the SDA line while SCL is held high indicates a STOP condition. All commands to the device must be followed by a STOP condition.
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FS6131
5.1.4. Data Valid The state of the SDA line represents valid data if the SDA line is stable for the duration of the high period of the SCL line after a START condition occurs. The data on the SDA line must be changed only during the low period of the SCL signal. There is one clock pulse per data bit. Each data transfer is initiated by a START condition and terminated with a STOP condition. The number of data bytes transferred between START and STOP conditions is determined by the master device, and can continue indefinitely. However, data that is overwritten to the device after the first eight bytes will overflow into the first register, then the second, and so on, in a first-in, firstoverwritten fashion.
5.1.5. Acknowledge When addressed, the receiving device is required to generate an acknowledge after each byte is received. The master device must generate an extra clock pulse to coincide with the acknowledge bit. The acknowledging device must pull the SDA line low during the high period of the master acknowledge clock pulse. Setup and hold times must be taken into account. The master must signal an end of data to the slave by not generating an acknowledge bit on the last byte that has been read (clocked) out of the slave. In this case, the slave must leave the SDA line high to enable the master to generate a STOP condition. 5.2 I2C-bus Operation All programmable registers can be accessed randomly or sequentially via this bi-directional two wire digital interface. The crystal oscillator does not have to run for communication to occur. The device accepts the following I2C-bus commands.
5.2.1. Slave Address After generating a START condition, the bus master broadcasts a seven-bit slave address followed by a R/W bit. The address of the device is:
A6 1 A5 0 A4 1 A3 1 A2 X A1 0 A0 0
where X is controlled by the logic level at the ADDR pin. The variable ADDR bit allows two different FS6131 devices to exist on the same bus. Note that every device on an I2C-bus must have a unique address to avoid bus conflicts. The default address sets A2 to 0 via the pull-down on the ADDR pin.
5.2.2. Random Register Write Procedure Random write operations allow the master to directly write to any register. To initiate a write procedure, the R/W bit that is transmitted after the seven-bit device address is a logic-low. This indicates to the addressed slave device that a register address will follow after the slave device acknowledges its device address. The register address is written into the slave's address pointer. Following an acknowledge by the slave, the master is allowed to write eight bits of data into the addressed register. A final acknowledge is returned by the device, and the master generates a STOP condition. If either a STOP or a repeated START condition occurs during a register write, the data that has been transferred is ignored.
5.2.3. Random Register Read Procedure Random read operations allow the master to directly read from any register. To perform a read procedure, the R/W bit that is transmitted after the seven-bit address is a logic-low, as in the register write procedure. This indicates to the addressed slave device that a register address will follow after the slave device acknowledges its device address. The register address is then written into the slave's address pointer.
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FS6131
Following an acknowledge by the slave, the master generates a repeated START condition. The repeated START terminates the write procedure, but not until after the slave's address pointer is set. The slave address is then resent, with the R/W bit set this time to a logic-high, indicating to the slave that data will be read. The slave will acknowledge the device address, and then transmits the eight-bit word. The master does not acknowledge the transfer but does generate a STOP condition.
5.2.4. Sequential Register Write Procedure Sequential write operations allow the master to write to each register in order. The register pointer is automatically incremented after each write. This procedure is more efficient than the random register write if several registers must be written. To initiate a write procedure, the R/W bit that is transmitted after the seven-bit device address is a logic-low. This indicates to the addressed slave device that a register address will follow after the slave device acknowledges its device address. The register address is written into the slave's address pointer. Following an acknowledge by the slave, the master is allowed to write up to eight bytes of data into the addressed register before the register address pointer overflows back to the beginning address. An acknowledge by the device between each byte of data must occur before the next data byte is sent. Registers are updated every time the device sends an acknowledge to the host. The register update does not wait for the STOP condition to occur. Registers are therefore updated at different times during a sequential register write.
5.2.5. Sequential Register Read Procedure Sequential read operations allow the master to read from each register in order. The register pointer is automatically incremented by one after each read. This procedure is more efficient than the random register read if several registers must be read. To perform a read procedure, the R/W bit that is transmitted after the seven-bit address is a logic-low, as in the register write procedure. This indicates to the addressed slave device that a register address will follow after the slave device acknowledges its device address. The register address is then written into the slave's address pointer. Following an acknowledge by the slave, the master generates a repeated START condition. The repeated START terminates the write procedure, but not until after the slave's address pointer is set. The slave address is then resent, with the R/W bit set this time to a logic-high, indicating to the slave that data will be read. The slave will acknowledge the device address, and then transmits all eight bytes of data starting with the initial addressed register. The register address pointer will overflow if the initial register address is larger than zero. After the last byte of data, the master does not acknowledge the transfer but does generate a STOP condition.
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FS6131
S
DEVICE ADDRESS
WA
REGISTER ADDRESS
A
DATA
AP
7-bit Receive Device Address START Command
Register Address Acknowledge WRITE Command From bus host to device
Data Acknowledge STOP Condition Acknowledge From device to bus host
Figure 13: Random Register Write Procedure
S
DEVICE ADDRESS
WA
REGISTER ADDRESS
AS
DEVICE ADDRESS
RA
DATA
AP
7-bit Receive Device Address START Command
Register Address Acknowledge WRITE Command From bus host to device
7-bit Receive Device Address Repeat START Acknowledge From device to bus host
Data Acknowledge READ Command STOP Condition NO Acknowledge
Figure 14: Sequential Register Write Procedure
S
DEVICE ADDRESS
WA
REGISTER ADDRESS
AS
DEVICE ADDRESS
RA
DATA
A
DATA
AP
7-bit Receive Device Address START Command
Register Address Acknowledge WRITE Command From bus host to device
7-bit Receive Device Address Repeat START Acknowledge From device to bus host
Data Acknowledge READ Command Acknowledge
Data NO Acknowledge STOP Command
Figure 15: Sequential Register Read Procedure
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FS6131
6.0 Programming Information
All register bits are cleared to zero on power-up. All register bits may be read back as written except STAT[1] (Bit 63).
Table 3: Register Map Address Bit 7 STAT[1]
(Bit 63)
Bit 6 STAT[0]
(Bit 62)
Bit 5 XLVTEN
(Bit 61) 0 = Fine Tune Inactive 1 = Fine Tune Active
Bit 4 CMOS
(Bit 60) 0 = PECL 1 = CMOS, Lock Status
Bit 3 XCT[3]
(Bit 59)
Bit 2 XCT[2]
(Bit 58)
Bit 1 XCT[1]
(Bit 57)
Bit 0 XCT[0]
(Bit 56)
00 = Crystal Loop - Lock Status
Byte 7
01 = Crystal Loop - Out of Range 10 = Main Loop - Phase Status 11 = Feedback Divider Output
VCXO Coarse Tune See Table 11
XLPDEN
(Bit 55)
XLSWAP
(Bit 54) 0 = Use with External VCXO 1 = Use with Internal VCXO
XLCP[1]
(Bit 53)
XLCP[0]
(Bit 52)
XLROM[2]
(Bit 51)
XLROM[1]
(Bit 50)
XLROM[0]
(Bit 49)
GBL
(Bit 48) 0 = No Clock Phase Adjust 1 = Clock Phase Delay
Byte 6
0 = Crystal Loop Operates 1 = Crystal Loop Powered Down
00 = 1.5A 01 = 5A 10 = 8A 11 = 24A Crystal Loop Control See Table 10
OUTMUX[1]
(Bit 47)
OUTMUX[0]
(Bit 46)
OSCTYPE
(Bit 45) 0 = Low Phase Jitter Oscillator 1 = FS6031 Oscillator
VCOSPD
(Bit 44) 0 = High Speed Range 1 = Low Speed Range
LFTC
(Bit 43) 0 = Short Time Constant 1 = Long Time Constant
EXTLF
(Bit 42) 0 = Internal Loop Filter 1 = External Loop Filter
MLCP[1]
(Bit 41)
MLCP[0]
(Bit 40) 00 = 1.5A 01 = 5A 10 = 8A 11 = 24A
00 = VCO Output
Byte 5
01 = Reference Divider Output 10 = Phase Detector Input 11 = VCXO Output
FBKDSRC[1]
(Bit 39)
FBKDSRC[0]
(Bit 38)
FBKDIV[13]
(Bit 37) 8192
FBKDIV[12]
(Bit 36) 4096
FBKDIV[11]
(Bit 35) 2048
FBKDIV[10]
(Bit 34) 1024
FBKDIV[9]
(Bit 33) 512
FBKDIV[8]
(Bit 32) 256
00 = Post Divider Output
Byte 4
01 = FBK Pin 10 = Post Divider Input 11 = FBK Pin M Counter
FBKDIV[7]
(Bit 31)
FBKDIV[6]
(Bit 30) 64
FBKDIV[5]
(Bit 29) 32 M Counter
FBKDIV[4]
(Bit 28) 16
FBKDIV[3]
(Bit 27) 8
FBKDIV[2]
(Bit 26) 4
FBKDIV[1]
(Bit 25) 2 A Counter - See Table 2
FBKDIV[0]
(Bit 24) 1
Byte 3
128
POST3[1]
(Bit 21)
POST3[1]
(Bit 20)
POST2[1]
(Bit 19)
POST2[0]
(Bit 18)
POST1[1]
(Bit 17)
POST1[0]
(Bit 16)
00 = Divide by 1
00 = Divide by 1 01 = Divide by 3 10 = Divide by 5 11 = Divide by 4
00 = Divide by 1 01 = Divide by 2 10 = Divide by 4 11 = Divide by 8
Byte 2
Reserved (0)
Reserved (0)
01 = Divide by 3 10 = Divide by 5 11 = Divide by 4
PDFBK
(Bit 15)
PDREF
(Bit 14) 0 = Reference Divider 1 = REF Pin
SHUT
(Bit 13) 0 = Main Loop Operates 1 = Main Loop Powered Down
REFDSRC
(Bit 12) 0 = VCXO
REFDIV[11]
(Bit 11)
REFDIV[10]
(Bit 10)
REFDIV[9]
(Bit 9)
REFDIV[8]
(Bit 8)
Byte 1
0 = Feedback Divider 1 = FBK Pin
2048 1 = Ref Pin
1024
512
256
REFDIV[7] Byte 0
(Bit 7) 128
REFDIV[6]
(Bit 6) 64
REFDIV[5]
(Bit 5) 32
REFDIV[4]
(Bit 4) 16
REFDIV[3]
(Bit 3) 8
REFDIV[2]
(Bit 2) 4
REFDIV[1]
(Bit 1) 2
REFDIV[0]
(Bit 0) 1
Rev. 4 | Page 16 of 44 | www.onsemi.com
FS6131
Table 4: Device Configuration Bits Name REFDSRC (Bit 12) SHUT (Bit 13) PDREF (Bit 14) PDFBK (Bit 15) Description REFerence Divider SouRCe Bit = 0 Crystal Oscillator (VCXO) Bit = 1 REF pin main loop SHUT down select Bit = 0 Disabled (main loop operates) Bit = 1 Enabled (main loop shuts down) Phase Detector REFerence source Bit = 0 Reference Divider Bit = 1 REF pin Phase Detector FeedBacK source Bit = 0 Feedback Divider Bit = 1 FBK pin FeedBacK Divider SouRCe Bit 39 = 0 Post Divider Output Bit 38 = 0 Bit 39 = 0 FBK pin Bit 38 = 1 Bit 39 = 1 VCO Output (Post Divider Input) Bit 38 = 0 Bit 39 = 1 FBK pin Bit 38 = 1 EXTernal Loop Filter select Bit = 0 Internal Loop Filter Bit = 1 EXTLF pin OSCillator TYPe Bit = 0 Low Phase Jitter Oscillator Bit = 1 FS6031 Compatible Oscillator OUTput MUltipleXer select Bit 47 = 0 Main Loop PLL (VCO Output) Bit 46 = 0 Bit 47 = 0 Reference Divider Output Bit 46 = 1 Bit 47 = 1 Phase Detector Input Bit 46 = 0 Bit 47 = 1 VCXO Output Bit 46 = 1 clock GobBLer control Bit = 0 No Clock Phase Adjust Bit = 1 Clock Phase Delay CLKP/CLKN output mode PECL Output Bit = 0 (positive-ECL output drive) CMOS Output / Bit = 1 Lock Status Indicator
FBKDSRC[1:0] (Bits 39-38)
EXTLF (Bit 42) OSCTYPE (Bit 45)
OUTMUX[1:0] (Bits 47-46)
GBL (Bit 48)
CMOS (Bit 60)
Rev. 4 | Page 17 of 44 | www.onsemi.com
FS6131
Table 5: LOCK/IPRG Pin Configuration Bits Name Description Crystal Loop Lock STATus Mode / Main Loop Phase Align STATus mode (see also Table 6) Bit 63 = 0 Crystal Loop Lock status: Bit 62 = 0 Locked or Unlocked Bit 63 = 0 Crystal Loop Lock status: Bit 62 = 1 Out of Range High or Low Bit 63 = 1 Main Loop Phase Align status Bit 62 = 0 Bit 63 = 1 Feedback Divider output Bit 62 = 1
STAT[1:0] (Bits 63-62)
Table 6: Lock Status CMOS 1 1 STAT [1] 0 0 STAT [0] 0 1 LOCK / IPRG PIN 1 0 0 1 STAT[1] Read 1 0 0 1 Status Locked Unlocked Out-of-Range: Low Out-of-Range: High
Table 7: Main Loop Tuning Bits Name VCOSPD (Bit 44) Description VCO SPeeD range select (see Table 16) Bit = 0 Bit = 1 High Speed Range Low Speed Range
Main Loop Charge Pump current Bit 41 = 0 Bit 40 = 0 MLCP[1:0] (Bits 41-40) Bit 41 = 0 Bit 40 = 1 Bit 41 = 1 Bit 40 = 0 Bit 41 = 1 Bit 40 = 1 LFTC (Bit 43) Current = 1.5A Current = 5A Current = 8A Current = 24A
Loop Filter Time Constant (internal) Bit = 0 Bit = 1 Short Time Constant: 13.5s Long Time Constant: 135s
Rev. 4 | Page 18 of 44 | www.onsemi.com
FS6131
Table 8: Divider Control Bits Name REFDIV[11:0] (Bits 11-0) FBKDIV[13:0] (Bits 37-24) Description REFerence DIVider (NR) FeedBacK DIVider (NF) FBKDIV[2:0] FBKDIV[13:3] POST Divider #1 (NP1) Bit 17 = 0 Bit 16 = 0 POST1[1:0] (Bits 17-16) Bit 17 = 0 Bit 16 = 1 Bit 17 = 1 Bit 16 = 0 Bit 17 = 1 Bit 16 = 1 POST Divider #2 (NP2) Bit 19 = 0 Bit 18 = 0 POST2[1:0] (Bits 19-18) Bit 19 = 0 Bit 18 = 1 Bit 19 = 1 Bit 18 = 0 Bit 19 = 1 Bit 18 = 1 POST Divider #3 (NP3) Bit 21 = 0 Bit 20 = 0 POST3[1:0] (Bits 21-20) Bit 21 = 0 Bit 20 = 1 Bit 21 = 1 Bit 20 = 0 Bit 21 = 1 Bit 20 = 1 Reserved (0) (Bits 23-22) Set these reserved bits to 0 Divide by 1 Divide by 3 Divide by 5 Divide by 4 Divide by 1 Divide by 3 Divide by 5 Divide by 4 Divide by 1 Divide by 2 Divide by 4 Divide by 8 A-Counter Value M-Counter Value
Rev. 4 | Page 19 of 44 | www.onsemi.com
FS6131
Table 9: Crystal Loop Tuning Bits Name Description Crystal Loop Charge Pump current Bit 53 = 0 Bit 52 = 0 XLCP[1:0] (Bits 53-52) Bit 53 = 0 Bit 52 = 1 Bit 53 = 1 Bit 52 = 0 Bit 53 = 1 Bit 52 = 1 XLROM[2:0] (Bits 51-49) XLVTEN (Bit 61) Current = 1.5A Current = 5A Current = 8A Current = 24A
Crystal Loop Divider ROM select and Crystal Oscillator Power-Down (see Error! Reference source not found.) Crystal Loop Voltage fine Tune ENable Bit = 0 Bit = 1 Disabled (fine tune is inactive) Enabled (fine tune is active)
Crystal Loop SWAP polarity Bit = 0 XLSWAP (Bit 54) Bit = 1 Use with an external VCXO that increases in frequency in response to an increasing voltage at the XTUNE pin. Use with a VCXO that increases in frequency in response to a decreasing voltage at the XTUNE pin. Use this setting for Internal VCXO
Crystal Loop Power Down Enable XLPDEN (Bit 55) Bit = 0 Bit = 1 XCT[3:0] (Bits 59-56) Disabled (crystal loop operates) Enabled (crystal loop is powered down)
Crystal Coarse Tune (see Table 11)
Table 10: Crystal Loop Control ROM XLROM [2] 0 0 0 0 1 1 1 1 XLROM [1] 0 0 1 1 0 0 1 1 XLROM [0] 0 1 0 1 0 1 0 1 VCXO Divider 1 3072 3156 2430 2500 4000 3375 Crystal oscillator power-down Crystal Frequency (MHz) 24.576 25.248 19.44 20.00 32.00 27.00
6.1 VCXO Coarse Tune The VCXO may be coarse tuned by a programmable adjustment of the crystal load capacitance via XCT[3:0]. The actual amount of frequency warping caused by the tuning capacitance will depend on the crystal used. The VCXO tuning capacitance includes an external 6pF load capacitance (12pF from the XIN pin to ground and 12pF from the XOUT pin to ground). The fine tuning capability of the VCXO can be enabled by setting the XLVTEN bit to a logic-one, or disabled by setting the bit to a logic-zero.
Rev. 4 | Page 20 of 44 | www.onsemi.com
FS6131
Table 11: VCXO Coarse Running Capacitance XCT[3] 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 XCT[2] 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 XCT[1] 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 XCT[0] 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 VCXO Tuning Capacitance (pf) 10.00 10.84 11.69 12.53 13.38 14.22 15.06 15.91 16.75 17.59 18.43 19.28 20.13 20.97 21.81 22.66
7.0 Electrical Specifications
Table 12: Absolute Maximum Ratings Parameter Supply Voltage, dc (VSS = ground) Input Voltage, dc Output Voltage, dc Input Clamp Current, dc (VI < 0 or VI > VDD) Output Clamp Current, dc (VI < 0 or VI > VDD) Storage Temperature Range (non-condensing) Ambient Temperature Range, Under Bias Junction Temperature Lead Temperature (soldering, 10s) Input Static Discharge Voltage Protection (MIL-STD 883E, Method 3015.7) Symbol VDD VI VO IIK IOK TS TA TJ Min. VSS-0.5 VSS-0.5 VSS-0.5 -50 -50 -65 -55 Max. 7 VDD+0.5 VDD+0.5 50 50 150 125 150 260 2 Units V V V mA mA C C C C kV
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These conditions represent a stress rating only, and functional operation of the device at these or any other conditions above the operational limits noted in this specification is not implied. Exposure to maximum rating conditions for extended conditions may affect device performance, functionality, and reliability.
CAUTION: ELECTROSTATIC SENSITIVE DEVICE
Permanent damage resulting in a loss of functionality or performance may occur if this device is subjected to a high-energy electrostatic discharge.
Rev. 4 | Page 21 of 44 | www.onsemi.com
FS6131
Table 13: Operating Conditions Parameter Supply Voltage Ambient Operating Temperature Range Crystal Resonator Frequency Crystal Resonator Load Capacitance Crystal Resonator Motional Capacitance Serial Data Transfer Rate PECL Mode Programming Current (LOCK/IPRG Pin High-Level Input Current) Output Driver Load Capacitance IIH CL Symbol VDD TA fXIN CXL CXM Parallel resonant, AT cut Parallel resonant, AT cut Standard mode PECL Mode 10 Conditions/Descriptions 5V 10% Min. 4.5 0 19.44 27 18 25 100 400 15 15 Typ. 5 Max. 5.5 70 28 Units V C MHz pF fF kb/s mA pF
Table 14: DC Electrical Specifications Parameter Overall Supply Current, Dynamic, (with Loaded Outputs) Supply Current, Static Serial Communication I/O (SDA, SCL) High-Level Input Voltage Low-Level Input Voltage Hysteresis Voltage * Input Leakage Current Low-Level Output Sink Current (SDA) Tristate Output Current Address Select Input (ADDR) High-Level Input Voltage Low-Level Input Voltage High-Level Input Current (pull-down) Low-Level Input Current Reference Frequency Input (REF, FBK) High-Level Input Voltage Low-Level Input Voltage Hysteresis Voltage Input Leakage Current VIH VIL Vhys II 3.5 VSS-0.3 500 -1 1 VDD+0.3 1.5 V V mV A VIH VIL IIH IIL VIH = VDD = 5.5V 2.4 VSS-0.3 5 -2 16 VDD+0.3 0.8 30 2 V V A A VIH VIL Vhys II IOL IZ VOL = 0.4V Outputs off Outputs off Outputs off -1 20 -10 32 10 3.5 VSS-0.3 2 1 VDD+0.3 1.5 V V V A mA A IDD IDDL fCLK = 66MHz ; CMOS Mode, VDD = 5.5V SHUT = 1, XLROM[2:0] = 7, XLPDEN = 1 VDD = 5.5V 100 12 mA mA Symbol Conditions/Description Min. Typ. Max. Units
Rev. 4 | Page 22 of 44 | www.onsemi.com
FS6131
Table 14: DC Electrical Specifications (Continued) Parameter Loop Filter Input (EXTLF) Input Leakage Current II EXTLF = 0 VO = 0.8V; EXTLF =1, MLCP[1:0] = 0 High-Level Output Source Current IOH VO = 0.8V; EXTLF =1, MLCP[1:0] = 1 VO = 0.8V; EXTLF =1, MLCP[1:0] = 2 VO = 0.8V; EXTLF =1, MLCP[1:0] = 3 VO = 4.2V; EXTLF =1, MLCP[1:0] = 0 Low-Level Output Sink Current IOL VO = 4.2V; EXTLF =1, MLCP[1:0] = 1 VO = 4.2V; EXTLF =1, MLCP[1:0] = 2 VO = 4.2V; EXTLF =1, MLCP[1:0] = 3 Crystal Oscillator Input (XIN) Threshold Bias Voltage High-Level Input Current Low-Level Input Current Crystal Loading Capacitance * Input Loading Capacitance * Crystal Oscillator Output (XOUT) High-Level Output Source Current Low-Level Output Sink Current VCXO Tuning I/O (XTUNE) High-Level Input Voltage Low-Level Input Voltage Hysteresis Voltage Input Leakage Current VIH VIL Vhys II XLPDEN = 0 VO = 0.8V; XLCP[1:0] = 0 High-Level Output Source Current IOH VO = 0.8V; XLCP[1:0] = 1 VO = 0.8V; XLCP[1:0] = 2 VO = 0.8V; XLCP[1:0] = 3 VO = 4.2V; XLCP[1:0] = 0 Low-Level Output Sink Current IOL VO = 4.2V; XLCP[1:0] = 1 VO = 4.2V; XLCP[1:0] = 2 VO = 4.2V; XLCP[1:0] = 3 Lock Indicator / PECL Current Program I/O (LOCK/IPRG) Low-Level Input Current High-Level Output Source Current Low-Level Output Sink Current Output Impedance * Short Circuit Source Current * Short Circuit Sink Current * IIL IOH IOL zOH zOL ISCH ISCL PECL Mode CMOS Mode; VO = 2.4V CMOS Mode; VO = 0.4V VO = 0.5VDD; output driving high VO = 0.5VDD; output driving low VO = 0V; shorted for 30s, max. VO = 5V; shorted for 30s, max. -1 -25 5 -38 9 66 76 -47 47 1 A mA mA mA mA Lock Status: Out of Range HIGH Lock Status: Out of Range LOW 3.2 VSS-0.3 1.0 -1 -1.5 -5 -8 -24 1.5 5 8 25 A A 1 VDD+0.3 0.3 V V V A IOH IOL VO = 0V, float XIN VO = 5V, float XIN -20 -20 -30 -40 -50 -50 mA mA VTH IIH IIL CL(xtal) CL(XIN) Outputs off; VIH = 5V Outputs off; VIL = 0V As seen by an external crystal connected to XIN and XOUT; VCXO tuning disabled As seen by an external clock driver on XOUT; XIN unconnected; VCXO disabled 1.5 10 -10 2.2 24 -19 10 20 3.5 30 -30 V mA mA pF pF -1 -1.5 -5 -8 -24 1.5 5 8 25 A A 1 A Symbol Conditions/Description Min. Type. Max. Units
Rev. 4 | Page 23 of 44 | www.onsemi.com
FS6131
Table 14: DC Electrical Specifications (Continued) Parameter Symbol Clock Outputs, CMOS Mode (CLKN, CLKP) High-Level Output Source Current Low-Level Output Sink Current Output Impedance * Short Circuit Source Current * Short Circuit Sink Current * Clock Outputs, PECL Mode (CLKN, CLKP) IPRG Current to Output Current Ratio Low-Level Output Sink Current Tristate Output Current IOL IZ IPRG input current = 15mA -10 1:4 60 10 mA A IOH IOL zOH zOL ISCH ISCL VO = 2.4V VO = 0.4V VO = 0.5VDD; output driving high VO = 0.5VDD; output driving low VO = 0V; shorted for 30s, max. VO = 5V; shorted for 30s, max. -45 15 -68 20 28 33 -100 100 mA mA mA mA Conditions/Description Min. Typ. Max. Units
Unless otherwise stated, VDD = 5.0V 10%, no load on any output, and ambient temperature range TA = 0C to 70C. Parameters denoted with an asterisk ( * ) represent nominal characterization data and are not production tested to any specific limits. MIN and MAX characterization data are 3 from typical. Negative currents indicate current flows out of the device.
Table 15: AC Timing Specifications Parameter Overall Output Frequency * fO(max) CMOS Outputs PECL Outputs Low Phase Jitter Oscillator (OSCTYPE = 0) VCOSPD = 0 VCO Frequency * fVCO VCOSPD = 1 FS6031 Compatible Oscillator (OSCTYPE = 1) VCOSPD = 0 VCOSPD = 1 Low Phase Jitter Oscillator (OSCTYPE = 0) VCOSPD = 0 VCO Gain * AVCO VCOSPD = 1 FS6031 Compatible Oscillator (OSCTYPE = 1) VCOSPD = 0 VCOSPD = 1 Loop Filter Time Constant * Rise Time * Fall Time * Lock Time (Main Loop) * Disable Time * tr tf LFTC = 0 LFTC = 1 CMOS Outputs, VO = 0.5V to 4.5V; CL = 15pF CMOS Outputs, VO = 4.5V to 0.5V; CL = 15pF Frequency Synthesis Line Locked Modes (8kHz reference) From falling edge of SCL for the last data bit (SHUT = 1 to 0) to output locked 130 78 13.5 135 1.1 0.8 200 10 10 s ns ns s ms s 125 75 MHz/V 40 40 230 140 40 40 160 100 MHz 130 230 MHz Symbol Conditions/Description Clock (MHz) Min. Typ. Max. Units
Rev. 4 | Page 24 of 44 | www.onsemi.com
FS6131
Table 15: AC Specifications (Continued)
Parameter Divider Modulus Feedback Divider Reference Divider NF NR NP1 Post Divider NP2 NP3 Clock Output (CLKP, CLKN) Duty Cycle *
Ratio of pulse width (as measured from rising edge to next falling edge at 2.5V) to one clock period Rising edges 50ms apart at 2.5V, relative to an ideal clock, CL=15pF, fREF=8kHz, NR=1, NF=193, NPx=64, CLF=0.054F, RLF=15.7k, CLP=1800pF, OSCTYPE=0, MLCP=3, XLROM=7 Rising edges 50ms apart at 2.5V, relative to an ideal clock, CL=15pF, fREF=15kHz, NR=1, NF=800, NPx=10, CLF=0.0246F, RLF=15.7k, CLP=820pF, OSCTYPE=0, MLCP=3, XLROM=7
Symbol
Conditions/Description
Clock (MHz)
Min.
Typ.
Max.
Units
FBKDIV[13:0] (See also Table 2) REFDIV[11:0] POST1[1:0] (See also Table 8) POST2[1:0] (See also Table 8) POST3[1:0] (See also Table 8)
8 1 1 1 1
16383 4095 8 5 5
100 1.544 12.00 25.175 100 200 1.544 12.00 25.175 100 200
47 270 160
54
%
Jitter, Long Term (y()) *
tj(LT)
On rising edges 5ms apart at 2.5V relative to an ideal clock, CL=15pF, fREF=31.5kHz, NR=1, NF=799, NPx=4, CLF=0.015F, RLF=15.7k, CLP=470pF, OSCTYPE=0, MLCP=3, XLROM=7 On rising edges 500s apart at 2.5V relative to an ideal clock, CL=15pF, CMOS mode, fXIN=27MHz, NF=200, NR=27, NPx=2 On rising edges 500s apart at 2.5V relative to an ideal clock, CL=15pF, PECL mode, fXIN=27MHz, NF=200, NR=27, NPx=1 From rising edge to next rising edge at 2.5V, CL=15pF, fREF=8kHz, NR=1, NF=193, NPx=64, CLF=0.054F, RLF=15.7k, CLP=1800pF, OSCTYPE=0, MLCP=3, XLROM=7 From rising edge to next rising edge at 2.5V, CL=15pF, fREF=15kHz, NR=1, NF=800, NPx=10, CLF=0.0246F, RLF=15.7k, CLP=820pF, OSCTYPE=0, MLCP=3, XLROM=7
ps 100 30 30 140 130 ps 105 340 270
Jitter, Period (peak-peak) *
tj(P)
From rising edge to next rising edge at 2.5V, CL=15pF, fREF=31.5kHz, NR=1, NF=799, NPx=4, CLF=0.015F, RLF=15.7k, CLP=470pF, OSCTYPE=0, MLCP=3, XLROM=7 From rising edge to next rising edge at 2.5V, CL=15pF, CMOS mode, fXIN=27MHz, NF=200, NR=27, NPx=2 From rising edge to next rising edge at 2.5V, CL=15pF, PECL mode, fXIN=27MHz, NF=200, NR=27, NPx=1
Unless otherwise stated, VDD = 5.0V 10%, no load on any output, and ambient temperature range TA = 0C to 70C. Parameters denoted with an asterisk ( * ) represent nominal characterization data at TA = 27C and are not production tested to any specific limits. MIN and MAX characterization data are 3 from typical.
Table 16: Serial Interface Timing Specifications Parameter Clock frequency Bus free time between STOP and START Set up time, START (repeated) Hold time, START Set up time, data input Hold time, data input Output data valid from clock Rise time, data and clock Fall time, data and clock High time, clock Low time, clock Set up time, STOP
Symbol fSCL tBUF tsu:STA thd:STA tsu:DAT thd:DAT tAA tR tF tHI tLO tsu:STO
Conditions/Description SCL
Min. 0 4.7 4.7 4.0
Max. 400
Units kHz s s s ns s
SDA SDA
Minimum delay to bridge undefined region of the falling edge of SCL to avoid unintended START or STOP
250 0 3.5 1000 300 4.0 4.7 4.0
s ns ns s s s
SDA, SCL SDA, SCL SCL SCL
Unless otherwise stated, VDD = 5.0V 10%, no load on any output, and ambient temperature range TA = 0C to 70C. Parameters denoted with an asterisk ( * ) represent nominal characterization data and are not production tested to any specific limits. MIN and MAX characterization data are 3 from typical.
Rev. 4 | Page 25 of 44 | www.onsemi.com
FS6131
~ ~
SCL
tsu:STA thd:STA tsu:STO
~ ~
SDA
~ ~
START
ADDRESS OR DATA VALID
DATA CAN CHANGE
STOP
Figure 16: Bus Timing Data
tF
tHI
tR
~ ~
SCL
tLO tsu:STA thd:STA thd:DAT tsu:DAT tsu:STO
~ ~
SDA IN
tAA tAA
tBUF
~ ~
SDA OUT
Figure 17: Data Transfer Sequence
Rev. 4 | Page 26 of 44 | www.onsemi.com
FS6131
Table 17: CLKP, CLKN Clock Outputs (CMOS Mode) Low Drive Current (mA) Voltage Voltage (V) (V) Min. Typ. Max. 0 0.2 0.5 0.7 1 1.2 1.5 1.7 2 2.2 2.5 2.7 3 3.5 4 4.5 5 5.5 0 7 18 24 32 37 43 46 51 53 55 56 57 58 59 59 0 11 27 36 49 56 66 72 79 83 88 91 93 95 97 99 100 0 15 37 50 69 80 95 103 115 122 130 135 140 146 149 152 155 158 0 0.5 1 1.5 2 2.5 2.7 3 3.2 3.5 3.7 4 4.2 4.5 4.7 5 5.2 5.5 High Drive Current (mA) Min. -58 -56 -55 -53 -49 -43 -40 -35 -31 -25 -21 -14 -8 0 Typ. -98 -96 -94 -91 -85 -77 -73 -67 -62 -54 -48 -39 -32 -21 -13 0 Max. -153 -150 -148 -142
Output Current (mA) 100 150 200
-135 -124 -119 -111 -105 -95 -87 -75 -67 -53 -44 -28 -17 0
50
0 -50 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
-100
-150
MIN
-200 Output Voltage (V)
TYP MAX
The data in this table represents nominal characterization data only.
Table 18: LOCK/IPRG Clock Output (CMOS Mode) Low Drive Current (mA) Voltage Voltage (V) (V) Min. Typ. Max. 0 0.2 0.5 0.7 1 1.2 1.5 1.7 2 2.2 2.5 2.7 3 3.5 4 4.5 5 5.5 0 4 9 12 16 19 23 25 28 29 32 33 34 35 35 36 0 4 10 13 18 21 26 29 32 35 38 39 42 45 46 46 47 0 4 11 15 21 25 30 33 38 41 45 48 51 56 60 62 63 63 0 0.5 1 1.5 2 2.5 2.7 3 3.2 3.5 3.7 4 4.2 4.5 4.7 5 5.2 5.5
High Drive Current (mA) Min. -35 -34 -33 -31 -28 -24 -23 -20 -17 -14 -11 -7 -4 0 Typ. -46 -45 -43 -41 -37 -33 -31 -28 -26 -22 -19 -15 -12 -8 -5 0 Max. -61 -60 -57 -54
Output Current (mA) 40 60 80
-50 -45 -42 -39 -36 -32 -29 -25 -22 -17 -14 -9 -5 0
20
0 -20 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
-40
-60
MIN
-80 Output Voltage (V)
TYP MAX
The data in this table represents nominal characterization data only.
Rev. 4 | Page 27 of 44 | www.onsemi.com
FS6131
8.0 Package Information for Both `Green'/'ROHS' and `Non-Green'
Table 19: 16-pin SOIC (0.150") Package Dimensions Dimension Inches Min. A A1 A2 B C D E e H h L 0.061 0.004 0.055 0.013 0.007 5 0.386 0.150 Max. 0.068 0.0098 0.061 0.019 0.0098 0.393 0.157 Millimeters Min. 1.55 0.102 1.40 0.33 0.191 9.80 3.81 Max. 1.73 0.249 1.55 0.49 0.249 9.98 3.99
0.050 BSC 0.230 0.010 0.016 0 0.244 0.016 0.035 8
1.27 BSC 5.84 0.25 0.41 0 6.20 0.41 0.89 8
Table 20: 16-pin SOIC (0.150") Package Characteristics Parameter Thermal Impedance, Junction to Free-Air Lead Inductance, Self Lead Inductance, Mutual Lead Capacitance, Bulk Symbol JA L11 L12 C11 Conditions/Description Air flow = 0 ft./min. Corner lead Center lead Any lead to any adjacent lead Any lead to VSS Typ. 108 4.0 3.0 0.4 0.5 Units C/W nH nH pF
9.0 Ordering Information
Part Number FS6131-01G-XTD FS6131-01G-XTP FS6131-01i-XTD FS6131-01i-XTP Package 16-pin (0.150") SOIC (green, ROHS or lead free packaging) 16-pin (0.150") SOIC (green, ROHS or lead free packaging) 16-pin (0.150") SOIC (small outline package) 16-pin (0.150") SOIC (small outline package) Shipping Configuration Tube/Tray Tape & Reel Tube/Tray Tape & Reel Temperature Range 0 C to 70 C (Commercial) 0 C to 70 C (Commercial) -40 C to 85 C (Industrial) -40 C to 85 C (Industrial)
Rev. 4 | Page 28 of 44 | www.onsemi.com
FS6131
10.0 Demonstration Software
MS Windows(R) based software is available from ON SEMICONDUCTOR that illustrates the capabilities of the FS6131.
10.1 Software Requirements * PC running MS Windows 95, 98, 98SE, ME, NT4, 2000, XP Home or Professional Editions. * 2.0MB available space on hard drive C:
10.2 Demo Program Operation Run the fs6131.exe program. A warning message will appear stating that the hardware is not connected. Click "Ignore". The FS6131 demonstration hardware is no longer supported by ON SEMICONDUCTOR. The opening screen is shown in Figure 18.
Figure 18: Opening Screen
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FS6131
10.2.1. Device Mode The device mode block presets the demo program to program the FS6131 either as a frequency synthesizer (a stand alone clock generator) or as a line-locked or genlock clock generator. Frequency Synthesis: For use as a stand alone clock generator. Note that the reference source is the on-chip crystal oscillator, the expected crystal frequency is 27MHz, and the voltage tune in the crystal oscillator (i.e. the VCXO) is disabled. The default output frequency (CLK freq.) requested is 100MHz, with a maximum error of 10ppm, or about 100Hz. The output stage defaults to CMOS mode. Line-Locked/Genlock: For use in a line-lock or genlock application. Note that the reference source is the REF pin, and that the expected reference frequency is 8kHz. The default output frequency requested is a 100x multiple of the reference frequency. 10.2.2. Example: Frequency Synthesizer Mode By default the demo program assumes the FS6131 is configured as a stand alone clock generator. Note that the reference source defaults to the on-chip crystal oscillator, the expected crystal frequency is 27MHz, and the voltage tune in the Crystal Oscillator block (i.e. the VCXO) is disabled. The default output frequency (CLK freq.) requested is 100MHz, with a maximum error of 10ppm, or about 100Hz. The Output Stage defaults to CMOS mode. The Loop Filter block is set to internal, and the Check Loop Stability switch is on. As an exercise, click on Calculate Solutions. The program takes into account all of the screen settings and calculates all possible combinations of reference, feedback and post divider values that will generate the output frequency (100MHz) from the input frequency (27MHz) within the desired tolerance (10ppm). A box will momentarily appear: "Calculating Solutions: Press cancel to stop with the solutions calculated so far." A number in the box will increment for every unique solution that is found. This example will create seven unique solutions, which are then displayed in a window in the lower right portion of the program screen. The best PLL performance is obtained by running the VCO at as high a speed as possible. The last three solutions show a VCO speed of 200MHz. Furthermore, good PLL performance is obtained with the smallest dividers possible, which means solution #4 should provide the best results.
Figure 19: Frequency Synthesizer Screen
Clicking on Solution #4 highlights the row, and clicking on Disp/Save Register Values provides a window with the final values of key settings. A click on OK then displays a second window containing register information per the register map. If the solutions are to be saved to a file, two formats are available: a text format for viewing, and a data format for loading into the FS6131.
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FS6131
Note: As an update to this data sheet, the FS6131 hardware is no longer available from ON SEMICONDUCTOR. 10.2.3. Example: Line-Locked Mode Selecting the line-locked/genlock option in the Device Mode block changes the program default settings. The Reference Source changes to the REF pin input, and a block appears to permit entry of the REF input frequency in MHz. A Desired Multiple block allows entry of the reference frequency multiplying factor used to generate the output frequency. Exercise: Change the ref pin frequency to 0.0315MHz, and alter the desired multiple to 800. Change the loop filter block to external, but leave the values for C1 and R alone. Click on Calculate Solutions. The program takes into account all of the current screen settings and calculates all possible combinations of reference, feedback and post divider values that will generate an output frequency from the input frequency (31.5kHz) multiplied by the desired multiple of 800. A box will appear: "No solutions were found! Do you want to retry calculations with the check loop stability option turned off?" Choose Yes. Another box may momentarily appear: "Calculating Solutions: Press cancel to stop with the solutions calculated so far." A number in the box will increment for every unique solution that is found. This example will create eight unique solutions, which are then displayed in a window in the lower right portion of the program screen. For best results, try to keep the PostDiv value multiplied by the FbkDiv value from getting larger than 5000 while running the VCO as much above 70MHz as possible. If a tradeoff must be made, it is better to run the VCO faster and allow the divider values to get large. Solution #3 provides a PostDiv value of 4 and a FbkDiv value of 800 for a combined value of 3200. The VCO is running at about 100MHz. Click on Solution #3 to highlight the row, then click on Suggest in the Loop Filter box to have the program choose loop filter values. Suggested values for an external loop filter are 4700pF and 47kW. Now reselect the Check Loop Stability box to turn this feature on. Clicking on Calculate Solutions regenerates the same solutions provided earlier, only this time the new loop filter values were used.
Figure 20: Line-Locked Screen
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FS6131
Clicking on Solution #3 highlights the row, and clicking on Disp/Save Register Values provides a window with the final values of key settings. A click on OK then displays a second window containing register information per the register map. If the solutions are to be saved to a file, two formats are available: a text format for viewing and a data format for loading into the FS6131.
Table 21: Sample Text Output
ON SEMICONDUCTOR - FS6131 Solution Text File Created: Today's Date, Today's Time Line-Locked / Genlock Mode Desired Multiple = 800 Source = 0.0315MHz Reference Pin External Loop Filter C1 = 4700pF R = 47kOhms Crystal Oscillator Voltage Tune Disabled Output Stage = CMOS Reference Divider = 1 Feedback Divider = 800 Post Divider =4 Charge Pump (uA) = 10 EXTLF =1 XLVTEN =0 XCT =7 CMOS =1 Register 0 Register 1 Register 2 Register 3 Register 4 Register 5 Register 6 Register 7 = 1H (1) = 40H (64) = 2H (2) = 20H (32) = 3H (3) = 26H (38) = 0H (0) = 17H (23)
11.0 Applications Information
A signal reflection will occur at any point on a PC-board trace where impedance mismatches exist. Reflections cause several undesirable effects in high-speed applications, such as an increase in clock jitter and a rise in electromagnetic emissions from the board. Using a properly designed series termination on each high-speed line can alleviate these problems by eliminating signal reflections. 11.1 PECL Output Mode If a PECL interface is desired, the transmission line must be terminated using a Thevenin, or dual, termination. The output stage can only sink current in the PECL mode, and the amount of sink current is set by a programming resistor on the LOCK/IPRG pin. Source current is provided by the pull-up resistor that is part of the Thevenin termination.
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FS6131
VCC VCC
Rp1 PECL Mode Output CLKP CLKN Ri from PLL IPRG zO zL zL
Rn1
LOAD
{
Rp2
Rn2
Figure 21: Thevenin Termination (PECL)
11.1.1. Example Calculation In PECL mode, the output driver does not source current, so the VIH value is determined by the ratios of the terminating resistors using the equation
V NMH = VCC x
R p1 R p1 + R p 2
where Rp1 is the pull-up resistor, Rp2 is the pull-down resistor and VNMH is the desired noise margin, and
V IH = VCC - V NMH
The resistor ratio must also match the line impedance via the equation
zL =
where zL is the line impedance. Combining these equations, and solving for Rp1 gives
R p1 R p 2 R p1 + R p 2
V NMH R p1 = z L + z L V -V NMH CC

If the load's VIH(min) = VCC - 0.6, choose a VNMH = 0.45V. If the line impedance is 75W, then Rp1 is about 82W. Substituting into the equation for line impedance and solving for Rp2 gives a value of 880W (choose 910W). To solve for the load's VIL, an output sink current must be programmed via the IPRG pin. If the desired VIH = VCC - 1.6, choose VCC - 2.0 for some extra margin. A sink current of 25mA through the 82W resistor generates a 2.05V drop. The sink current is programmed via the IPRG pin, where the ratio of IPRG current to output sink current is 1:4. An IPRG programming resistor of 750W at VDD = 5V generates 6.6mA, or about 27mA output sink current.
11.2 CMOS Output Mode If a CMOS interface is desired, a transmission line is typically terminated using a series termination. Series termination adds no dc loading to the driver, and requires less power than other resistive termination methods. In addition, no extra impedance exists from the signal line to a reference voltage, such as ground.
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FS6131
zO DRIVER LINE zL
RS
RECEIVE
Figure 22: Series Termination (CMOS)
As shown in Figure 22, the sum of the driver's output impedance (zO) and the series termination resistance (RS) must equal the line impedance (zL). That is,
RS = z L - zO
When the source impedance (zO+RS) is matched to the line impedance, then by voltage division the incident wave amplitude is one-half of the full signal amplitude.
Vi = V
( z O + RS ) V = ( z O + RS ) + z L 2
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FS6131
However, the full signal amplitude may take up to twice as long as the propagation delay of the line to develop, reducing noise immunity during the half-amplitude period. Note that the voltage at the receive end must add up to a signal amplitude that meets the receiver switching thresholds. The slew rate of the signal may be reduced due to the additional RC delay of the load capacitance and the line impedance. Also, note that the output driver impedance will vary slightly with the output logic state (high or low). 11.3 Serial Communications Connection of devices to a standard-mode implementation of the I2C-bus is similar to that shown in Figure 23. Selection of the pull-up resistors (RP) and the optional series resistors (RS) on the SDA and SCL lines depends on the supply voltage, the bus capacitance and the number of connected devices with their associated input currents. Control of the clock and data lines is done through open drain/collector current-sink outputs, and thus requires external pull-up resistors on both lines. A guideline is
RP <
tr 2 x Cbus
where tr is the maximum rise time (minus some margin) and Cbus is the total bus capacitance. Assuming an I2C controller and eight to ten other devices on the bus, including this one, results in values in the 5kW to 7kW range. Use of a series resistor to provide protection against high voltage spikes on the bus will alter the values for RP.
SDA SCL
(optional)
RP
RP
RS
(optional)
RS
(optional)
RS
(optional)
RS
Data In Clock Out Data Out Clock In
Data In
Data Out
TRANSMITTER
RECEIVER
Figure 23: Connections to the Serial Bus
11.3.1. For More Information
2 2 More information on the I C -bus can be found in the document The I C-bus And How To Use It (Including Specifications), available from Philips Semiconductors at http://www-us2.semiconductors.philips.com.
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FS6131
12.0 Device Application: Stand-Alone Clock Generation
The length of the reference and feedback dividers, their granularity and the flexibility of the post divider make the FS6131 the most flexible monolithic stand-alone PLL clock generation device available. The effective block diagram of the FS6131 when programmed for stand-alone mode is shown in Figure 24. The source of the feedback divider in the stand-alone mode is the output of the VCO. By dividing the input reference frequency down by reference divider (NR), then multiplying it up in the main loop through the feedback divider (NF), and finally dividing the main loop output frequency by the post divider (NPx), we have the defining relationship for this mode. The equation for the output clock frequency (fCLK) can be written as
N f CLK = f REF F N R
1 N Px

where the reference source frequency (fREF) can be either supplied by the VCXO or applied to the REF pin. Great flexibility is permitted in the programming of the FS6131 to achieve exact desired output frequencies since three integers are involved in the computation. 12.1 Example Calculation A Visual BASIC program is available to completely program the FS6131 based on the given parameters. Suppose that the reference source frequency is 14.318MHz and the desired output frequency is 100MHz. First, factor the 14.318MHz reference frequency (which is four times the NTSC television color sub-carrier) into prime numbers. The exact expression is
f REF
2 7 1 5 2 x3 x5 x7 = 14318181.81 = 11
LFTC
CLF CLP
XTUNE
(optional)
XCT[3:0], XLVTEN
Control ROM VCXO Divider
XLROM[2:0] XLPDEN, XLSWAP
CRYSTAL LOOP
XLCP[1:0]
XIN VCXO XOUT
(optional)
Internal Loop Filter
RLF
PhaseFrequency Detector
UP
EXTLF
EXTLF STAT[1:0] RIPRG
Charge Pump
DOWN
(optional)
Lock Detect
REFDIV[11:0]
CMOS
LOCK/ IPRG
(optional)
REF
(fREF)
REFDSRC
Reference Divider
(NR)
MLCP[1:0] PDREF UP
VCOSPD, OSCTYPE
GBL
POST3[1:0] POST2[1:0] POST1[1:0]
FBK
PDFBK
PhaseFrequency Detector
Charge Pump
DOWN
Voltage Controlled Oscillator
Clock Gobbler
OM[1:0]
Post Divider (NPx) CMOS/PECL Output
CLKP
(fCLK)
CLKN
ADDR Feedback Divider (NF) SCL SDA I2C Interface
FBKDSRC[1:0]
(fVCO)
Registers
MAIN LOOP
FBKDIV[14:0]
FS6131
Figure 24: Block Diagram: Stand-Alone Clock Generation
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FS6131
Next, express the output and input frequencies as a ratio of fCLK to fREF, where fCLK has also been converted to a product of prime numbers.
f CLK 100000000.00 2 8 x 58 = =5271 f REF 14318181.81 2 x 3 x 5 x 7 11
Simplifying the above equation yields
(
)
f CLK 2 3 x 51 x 11 = f REF 32 x 7
(
(
)
)
Deciding how to apportion the denominator integers between the reference divider and the post divider is an iterative process. To obtain the best performance, the VCO should be operated at the highest frequency possible without exceeding its upper limit of 230MHz. (see Table 15). The VCO frequency (fVCO) can be calculated by
f VCO = f REF x
NF NR
Recall that the reference divider can have a value between 1 and 4096, but the post divider is limited to values derived from
N Px = N P1 x N P 2 x N P 3
where the values NP1, NP2 and NP3 are found in Table 8. In this example, the smallest integer that can be removed from the denominator of Eqn. 2 is three. Set the post divider at NPx=3, and the ratio of fCLK to fREF becomes (from Eqn. 1)
f CLK 2 3 x 51 x 11 1 = x (3 x 7 ) f REF 3
Unfortunately, a post divider modulus of three requires a VCO frequency of 300MHz, which is greater than the allowable fVCO noted in Table 15. For the best PLL performance, program the post divider modulus to allow the VCO to operate at a nominal frequency that is at least 70MHz but less then 230MHz. Therefore, the reference divider cannot be reduced below the modulus of 327 (or 63) as shown in Eqn. 2. However, the VCO can still be operated at a frequency higher than fCLK. Multiplying both the numerator and the denominator by two does not alter the output frequency, but it does increase the VCO frequency.
(
)
f CLK N F 2 3 x 51 x 11 x 2 1 880 1 1 = x = x= x f REF N R N Px 2 63 2 32 x 7
(
(
)
)
As Eqn. 3 shows, the VCO frequency can be doubled by multiplying the feedback divider by two. Set the post divider to two to return the output frequency to the desired modulus. These divider settings place the VCO frequency at 200MHz.
12.2 Example Programming To generate 100.000MHz from 14.318MHz, program the following (refer to Figure 24): * Set the reference divider input to select the VCXO via REFDSRC=0 * Set the PFD input to select the reference divider and the feedback divider via PDREF=0 and PDFBK=0 * Set the reference divider (NR) to a modulus of 63 via REFDIV[11:0] * Set the feedback divider input to select the VCO via FBKDSRC=1 * Set the feedback divider (NF) to a modulus of 880 via FBKDIV[14:0] * Set NP1=2, NP2=1 and NP3=1 for a combined post divider modulus of NPx=2 via POST1[1:0], POST2[1:0] and POST3[1:0]. * Select the internal loop filter via EXTLF=0 * Set XLVTEN=0 and XLPDEN=1 to disable the VCXO fine tune and the crystal loop phase frequency detector * Set VCOSPD=0 to select the VCO high speed range
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FS6131
13.0 Device Application: Line-Locked Clock Generation
Line-locked clock generation, as used here, refers to the process of synthesizing a clock frequency that is some integer multiple of the horizontal line frequency in a graphics system. The FS6131 is easily configured to perform that function, as shown in Figure 25. A line reference signal (fHSYNC) is applied to the REF input for direct application to the main loop PFD. The feedback divider (NF) is programmed for the desired number of output clocks per line. The source for the feedback divider is selected to be the output of the post divider (NPx) so that the edges of the output clock maintain a consistent phase alignment with the line reference signal. The modulus of the post divider should be selected to maintain a VCO frequency that is comfortably within the operating range noted in Table 15.
13.1 Example Calculation A Visual BASIC program is available to completely program the FS6131 based on the given parameters. Suppose that we wish to reconstruct the pixel clock from a VGA source. This is a typical requirement of an LCD projection panel application. First, establish the total number of pixel clocks desired between horizontal sync (HSYNC) pulses. The number of pixel clocks is known as the horizontal total, and the feedback divider is programmed to that value. In this example, choose the horizontal total to be 800. Next, establish the frequency of the HSYNC pulses (fHSYNC) on the line reference signal for the video mode. In this case, let fHSYNC=31.5kHz. The output clock frequency fCLK is calculated to be:
f CLK = f HSYNC x N F = 31.5kHz x 800 = 25.175MHz
LFTC
CLF CLP
XTUNE
(optional)
XCT[3:0], XLVTEN
Control ROM VCXO Divider
XLROM[2:0] XLPDEN, XLSWAP
CRYSTAL LOOP
XLCP[1:0]
XIN VCXO XOUT
(optional)
Internal Loop Filter
RLF
PhaseFrequency Detector
UP
EXTLF
EXTLF STAT[1:0] RIPRG
Charge Pump
DOWN
(optional)
Reference HSYNC
REFDIV[11:0]
Lock Detect REF
(fREF)
REFDSRC POST3[1:0], POST2[1:0], POST1[1:0]
CMOS
LOCK/ IPRG
(optional)
Reference Divider
(NR)
MLCP[1:0] PDREF UP
VCOSPD, OSCTYPE
GBL
FBK
PDFBK
PhaseFrequency Detector
Charge Pump
DOWN
Voltage Controlled Oscillator
Clock Gobbler
OM[1:0]
Post Divider (NPx) CMOS/PECL Output
CLKP
(fCLK)
CLKN
ADDR Feedback Divider (NF) SCL SDA I2C Interface
FBKDSRC[1:0]
(fVCO)
Registers
MAIN LOOP
FBKDIV[14:0]
FS6131
Figure 25: Block Diagram: Line-Locked Clock Generation
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FS6131
However, the 31.5kHz line reference signal is too low in frequency for the internal loop filter to be used. A series combination of a 0.015mF capacitor and a 15kW resistor from power (VDD) to the EXTLF pin provides an external loop filter. A 100pF to 220pF capacitor in parallel with the combination may improve the filter performance. For the best PLL performance, program the post divider modulus to allow the VCO to operate at a nominal frequency that is at least 70MHz but less than 230MHz. The VCO frequency (fVCO) can be calculated by
f VCO = f HSYNC x N F x N Px
Setting the post divider equal to four (NPx=4) is a reasonable solution, although there are a number of values that will work. Try to keep
N F x N Px < 5000
to avoid divider values from becoming too large. These settings place the VCO frequency at about 100MHz. Calculate the ideal charge pump current (Ipump) as
I pump =
2N N f HSYNC x 2 F Px 15kHz Rlf C lf AVCO
where Rlf is the external loop filter series resistor, Clf is the external loop filter series capacitor and AVCO is the VCO gain. The VCO gain is either: AVCO=125MHz/V if the high range is selected, or AVCO=75MHz/V if the low range is selected. See Table 15 for more information on the VCO range. With fhsync=31.5kHz, Clf=0.015mF, Rlf=15kW, NF=800, NPx=4, and AVCO=125MHz/V, the charge pump current is 39.3mA. A 220pF cap across the entire loop filter is also helpful.
13.2 Example Programming To generate 800 pixel clocks between HSYNC pulses occurring on the line reference signal every 31.5kHz, program the following (refer to Figure 26): * Clear the OSCTYPE bit to 0 * Turn off the crystal oscillator via XLROM=7 * Set the PFD inputs to select the REF pin and the feedback divider via PDREF=1 and PDFBK=0 * Set the feedback divider input to select the post divider via FBKDSRC=0 * Set the feedback divider (NF) to a modulus of 800 (the desired number of pixel clocks per line) via FBKDIV[14:0] * Set NP1=4, NP2=1 and NP3=1 for a combined post divider modulus of NPx=4 via POST1[1:0], POST2[1:0] and POST3[1:0]. * Select the external loop filter via EXTLF=1 * Set XLVTEN=0 and XLPDEN=1 to disable the VCXO fine tune and the crystal loop phase frequency detector * Set VCOSPD=1 to select the VCO low speed range * Set MLCP[1:0] to 3 to select the 32mA range The output clock frequency fCLK is 25.175MHz, with an internal VCO frequency of 100.8MHz. Note that the crystal loop was unused in this application.
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FS6131
14.0 Device Application: Genlocking
Genlocking refers to the process of synchronizing the horizontal sync pulses (HSYNC) of a target graphics system to the HSYNC of a source graphics system. In a genlocked mode, the FS6131 increases (or decreases) the frequency of the VCO until the FBK input is frequency matched and phase-aligned to the frequency applied to the REF input. Since the feedback divider is within the graphics system and the graphics system is the source of the signal applied to the FBK input of the FS6131, the graphics system is effectively synchronized to the REF input as shown in Figure 26. To configure the FS6131 for genlocking, the REF input (pin 12) and the FBK input (pin 13) are switched directly onto the feedback input of the PFD. The reference and feedback dividers are not used. The output clock frequency is:
f CLK = f HSYNC x horizontal total
The only remaining task is to select a post divider modulus (NPx) that allows the VCO frequency to be within its nominal range.
14.1 Example Calculation A Visual BASIC program is available to completely program the FS6131 based on the given parameters. The FS6131 is being used to genlock an LCD projection panel system to a VGA card-generated HSYNC. The total number of pixel clocks generated by the VGA card, known as the horizontal total, are 800. Therefore, the LCD panel graphics system that is clocked by the FS6131 is set to divide the output clock frequency (fCLK) by 800. The input HSYNC reference frequency (fHSYNC) is 15kHz.
LFTC
CLF CLP
XTUNE
(optional)
XCT[3:0], XLVTEN
Control ROM VCXO Divider
XLROM[2:0] XLPDEN, XLSWAP
CRYSTAL LOOP
XLCP[1:0]
XIN VCXO XOUT
(optional)
Internal Loop Filter
RLF
PhaseFrequency Detector
UP
EXTLF
EXTLF STAT[1:0] RIPRG
Charge Pump
DOWN
(optional)
Reference HSYNC
REFDIV[11:0]
Lock Detect REF
(fCLK)
REFDSRC POST3[1:0], POST2[1:0], POST1[1:0]
CMOS
LOCK/ IPRG
(optional)
Reference Divider
(NR)
MLCP[1:0] PDREF UP
VCOSPD, OSCTYPE
GBL
FBK
PDFBK
PhaseFrequency Detector
Charge Pump
DOWN
Voltage Controlled Oscillator
Clock Gobbler
OM[1:0]
Post Divider (NPx) CMOS/PECL Output
CLKP
(fCLK)
CLKN
ADDR Feedback Divider (NF) SCL SDA I2C Interface
FBKDSRC[1:0]
(fVCO)
Registers
FBKDIV[14:0]
MAIN LOOP
FS6131
System HSYNC Video Graphics System Clock In
Figure 26: Block Diagram: Genlocking
Rev. 4 | Page 40 of 44 | www.onsemi.com
FS6131
The output clock frequency is calculated as
f CLK = 15kHz x 800 = 12.0MHz
For best performance, program the post divider (NPx) modulus to allow the VCO to operate at a nominal frequency that is at least 70MHz but less than 230MHz. The VCO frequency (fVCO) can be calculated by
f VCO = f CLK N Px
Selecting the post divider modulus of NPx=6 is a reasonable solution, although there are a number of values that will work. Try to keep
N F x N Px < 5000
to avoid divider values from becoming too large. The settings place the VCO frequency at about 72MHz. Calculate the ideal charge pump current (Ipump) as
I pump =
2N N f HSYNC x 2 F Px 15kHz Rlf C lf AVCO
where Rlf is the external loop filter series resistor, Clf is the external loop filter series capacitor and AVCO is the VCO gain. The VCO gain is either AVCO=125MHz/V if the high range is selected, or AVCO=75MHz/V if the low range is selected. See Table 15 for more information on the VCO range. With fhsync=15kHz, Clf=0.015mF, Rlf=15kW, NF=800, NPx=6, and AVCO=125MHz/V, the charge pump current is 24mA. A 220pF cap across the entire loop filter is also helpful.
14.2 Example Programming To generate 800 pixel clocks between HSYNC pulses occurring on the line reference signal every 15kHz, program the following (refer to Figure 26): * Clear the OSCTYPE bit to 0 * Turn off the crystal oscillator via XLROM=7 * Set the PFD inputs to select the REF and FBK pins via PDREF=1 and PDFBK=1 * Set NP1=2, NP2=3 and NP3=1 for a combined post divider modulus of NPx=6 via POST1[1:0], POST2[1:0] and POST3[1:0]. * Select the external loop filter via EXTLF=1 * Set XLVTEN=0 and XLPDEN=1 to disable the VCXO fine tune and the crystal loop phase frequency detector * Set VCOSPD=1 to select the VCO low speed range * Set MLCP[1:0] to 3 to select the 32mA range The output clock frequency fCLK is 12MHz, with an internal VCO frequency of 72MHz. Note that the crystal loop was unused in this application.
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FS6131
15.0 Device Application: Telecom Clock Regenerator
The FS6131 can be used as a clock regenerator as shown in Figure 28. This mode uses the VCXO in its own phase-locked loop, referred to as the crystal loop. The VCXO provides a "de-jittered" multiple of the reference frequency at the REF pin (usually 8kHz in telecom applications) for use by the main loop. In essence, the crystal loop "cleans up" the reference signal for the main loop. The control ROM for the VCXO divider is preloaded with the most common ratios to permit locking of most standard telecommunications crystals to an 8kHz signal applied to the REF pin. The de-jittered multiple of the reference frequency from the VCXO is then supplied to the reference divider in the main loop. The reference divider, along with the feedback divider, can be programmed to achieve the desired output clock frequency.
15.1 Example Calculation A Visual BASIC program is available to completely program the FS6131 based on the given parameters. In this example, an 8kHz reference frequency is supplied to the FS6131 and an output clock frequency of 51.84MHz is desired. First, select the frequency at which the VCXO will operate from Table 10. The table shows the external crystal frequency options available to choose from, since the VCXO runs at the crystal frequency. While the main loop can be programmed to work with any of the frequencies in the table, the best performance will be achieved with the highest frequency at the main loop PFD. The frequency at the main loop PFD (fMLpfd) is the VCXO frequency (fVCXO) divided by the main loop reference divider (NR).
f MLpfd =
f VCXO NR
LFTC
CLF CLP
XTUNE
(optional)
XCT[3:0], XLVTEN
Control ROM VCXO Divider
XLROM[2:0] XLPDEN, XLSWAP
CRYSTAL LOOP
XLCP[1:0]
XIN VCXO XOUT
(optional)
Internal Loop Filter
RLF
PhaseFrequency Detector
UP
EXTLF
EXTLF STAT[1:0] RIPRG
Charge Pump
DOWN
(optional)
8kHz IN (typical)
Lock Detect
REFDIV[11:0]
CMOS
LOCK/ IPRG
(optional)
REF
(fREF)
REFDSRC
Reference Divider
(NR)
MLCP[1:0] PDREF UP
VCOSPD, OSCTYPE
GBL
POST3[1:0], POST2[1:0], POST1[1:0]
FBK
PDFBK
PhaseFrequency Detector
Charge Pump
DOWN
Voltage Controlled Oscillator
Clock Gobbler
OM[1:0]
Post Divider (NPx) CMOS/PECL Output
CLKP
(fCLK)
CLKN
ADDR Feedback Divider (NF) SCL SDA I2C Interface
FBKDSRC[1:0]
(fVCO)
Registers
MAIN LOOP
FBKDIV[14:0]
FS6131
Figure 27: Block Diagram: Telecom Clock Generator
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FS6131
The goal is to choose the highest crystal frequency from Table 10 that generates the smallest value of NR. The equation establishing the output frequency (fCLK) as a function of the input VCXO frequency is
f CLK N =F f VCXO N R
where NF is the feedback divider modulus. Choose a few different crystal frequencies from Table 10 and factor both the input VCXO and output clock frequencies into prime numbers. Look for the factors that will give the smallest modulus for NR with the largest FVCXO. The output and VCXO frequencies and the reduced factors from Eqn. 1 are in Table 22.
Table 22: Clock Regenerator Example
A 19.44MHz crystal provides the smallest modulus for NR (NR=3) with the highest crystal frequency. Finally, choose a post divider (NPx) modulus that keeps the VCO frequency in its most comfortable range. The VCO frequency (fVCO) can be calculated by
f VCO = f CLK N Px
Selecting an overall modulus of NPx=3 sets the VCO frequency at 155.52MHz when the loop is locked.
15.2 Example Programming To generate a de-jittered output frequency of 51.84MHz from an 8kHz reference, program the following (refer to Figure 27): * Program the VCXO control ROM to 3 via XLROM[2:0] to select an external 19.44MHz crystal * Enable the VCXO fine tune via XLVTEN=1 * Enable the crystal loop PFD via XLPDEN=0 and XLSWAP=0 * Set the reference divider input to select the VCXO via REFDSRC * Set the PFD input to select the reference divider and the feedback divider via PDREF and PDFBK * Set the reference divider (NR) to a modulus of 3 via REFDIV[11:0] * Set the feedback divider input to select the VCO via FBKDSRC * Set the feedback divider (NF) to a modulus of 8 via FBKDIV[14:0] * Set NP1=1, NP2=3 and NP3=1 for a combined post divider modulus of NPx=3 via POST1[1:0], POST2[1:0] and POST3[1:0]. * Select the internal loop filter via EXTLF * Set VCOSPD=0 to select the VCO high speed range These settings provide the highest frequency at the main loop phase frequency detector of 6.48MHz. The use of a 19.44MHz crystal requires that XLROM[2:0] be set to three as shown in Table 10.
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FS6131
16.0 Revision History
Revision 3 4 Date January 2008 May 2008 Modification Moving into new AMIS template Moving into ON Semiconductor template
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